1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device and a method of writing data into the same.
2. Description of the Related Art
A nonvolatile semiconductor memory device is known, such as a flash memory of an NOR type in which flash memory cells using CHE (Channel Hot Electron) are arranged in a matrix. FIG. 1 is a block diagram showing the configuration of a conventional nonvolatile semiconductor memory device 101. The nonvolatile semiconductor memory device 101 contains a memory cell array 102, a decoder 103, a column switch circuit 104, a power supply circuit 105, a write circuit 106, a sense amplifier circuit 107, an address data buffer 108 and a control circuit 110.
The memory cell array 102 contains a plurality of memory cells (not shown) arrayed in a matrix, a plurality of bit lines (not shown) extending in a Y-direction and connected to the column switch circuit 104, a plurality of word lines (not shown) extending in an X-direction and connected to the decoder 103, and a plurality of source lines (not shown) extending in the Y-direction and grounded. The memory cell is a flash memory cell of an NOR type that uses CHE (Channel Hot Electron). The memory cell array 102 is divided into a plurality of regions 102-0 to 102-15 in accordance with the number of bits of a data, for example, 16 bits.
The decoder 103 selects as a selection word line, one from among a plurality of word lines in accordance with an address signal from the address data buffer 108. The column switch circuit 104 selects as a selection bit line, one from among the plurality of bit lines in each of the plurality of regions 102-0 to 102-15 in accordance with the address signal from the address data buffer 108 through the decoder 103. That is, in the example shown in FIG. 1, a total of 16 selection bit lines are selected at a same time. A selection cell as one of the plurality of memory cells is determined on the basis of the selection word line and the selection bit line.
The power supply circuit 105 applies a word line voltage (gate voltage) determined in accordance with a control signal from the control circuit 110, to the selection word line through the decoder 103. Also, the power supply circuit 105 has a function of a charge pump for supplying a write current to the write circuit 106. The write circuit 106 supplies the write current to each of the plurality of selection bit lines through the column switch circuit 104. Thus, a data is written to each of 16 selection cells.
The sense amplifier circuit 107 outputs a write state (a threshold voltage) of the selection cell to the control circuit 110 through the address data buffer 108. The address data buffer 108 transiently stores the data. The control circuit 110 outputs the address signal of the memory cells to which the write operation is performed and the write data to the address data buffer 108 and the control signal to the power supply circuit 105.
FIG. 2 is a block diagram showing the detailed configuration of the conventional nonvolatile semiconductor memory device. It should be noted that in FIG. 2, the sense amplifier circuit 107 and the address data buffer 108 are omitted.
In the memory cell array 102, the plurality of regions 102-0 to 102-15 have a plurality of common word lines W0 to Wn (n is an integer, and hereinafter, it is similar). Also, each 102-i (i=an integer of 0 to 15, and hereinafter, it is similar) of the plurality of regions 102-0 to 102-15 has a plurality of memory cells MCi arrayed in a matrix and a plurality of bit lines BLi connected to the column switch circuit 104.
The decoder 103 contains a row decoder 131 and a column decoder 132. The row decoder 131 selects the selection word line Ws from among the plurality of word lines W0 to Wn in accordance with the address signal from the control circuit 110. The column decoder 132 decodes the address signal from the control circuit 110 and supplies to the column switch circuit 104. The column switch circuit 104 selects the selection bit line BLi from among the plurality of bit lines BLi in accordance with the decoded address signal in each region 102-i. 
The write circuit 106 contains a plurality of write circuits 161-0 to 161-15. Each write circuit 161-i is used for the region 102-i, and connected to the selection bit line BLi of the region 102-i through the column switch circuit 104. Each write circuit 161-i supplies the write current to the selection bit line BLi in accordance with the write data.
The control circuit 110 contains a write control circuit 121 and a detecting circuit 122. The detecting circuit 122 detects the number of the memory cells to which the write operation is performed at a same time in accordance with the address signal and the write data. Then, the detecting circuit 122 outputs a detection signal indicating the number of memory cells, the address signal and the write data to the write control circuit 121. The write control circuit 121 controls the operations of the plurality of write circuits 161-0 to 161-15 in accordance with the detection signal, the address signal and the write data. Also, the write control circuit 121 outputs the address signal to the decoder 103, and outputs the control signal to the power supply circuit 105.
The power supply circuit 105 contains a gate boosting circuit 151 and a drain boosting circuit 152. The gate boosting circuit 151 applies a word line voltage (gate voltage) corresponding to the control signal to the selection word line W through the decoder 103 in accordance with the control signal. The drain boosting circuit 152 supplies the write current to the write circuit 106.
In the nonvolatile semiconductor memory device, there is a case that in the write operation, the plurality of memory cells are selected and the write operation is performed on the selected memory cells at a same time. In such a case, the number of the memory cells to which the write operation can be performed at the same time is limited in accordance with a current drive performance of the power supply circuit (the drain boosting circuit 152 in case of FIG. 2). In particular, in the nonvolatile semiconductor memory device of the NOR type that uses the CHE, the write current flowing through the memory cell in the write operation is relatively greater than that of the nonvolatile semiconductor memory device that does not use the CHE. Thus, a limit is caused due to the current drive performance of the power supply circuit.
FIG. 3 is a diagram showing a write sequence of the conventional nonvolatile semiconductor memory device of the NOR type that uses the CHE and has the configuration shown in FIGS. 1 and 2. The vertical axis indicates voltage, and the horizontal axis indicates time. The line DC (solid line) shows change of voltage applied to the word line, namely, the control gate of the memory cell. FIG. 4 is a block diagram showing a part of the configuration of FIG. 2. FIGS. 5 and 6 are timing charts showing the write data shown in FIG. 4.
With reference to FIG. 4, when the data is written into the memory cells for 16 bits, data signals D0 to D15 are supplied to the detecting circuit 122 at the same time. The data signals D0 to D15 at that time are supplied between a time t01 and a time t02, as shown in FIG. 5. The detecting circuit 122 refers to the data signals D0 to D15 between the time t01 and the time t02 and detects the number of memory cells into which the write operations are performed at the same time is 16. Then, the detecting circuit 122 outputs a detection signal indicating 16 to the write control circuit 121 together with the data signals D0 to D15.
Because of the limit resulting from the current drive performance of the power supply circuit 105, the number of the memory cells into which the write operation can be performed at one time is set to 8. Thus, the write control circuit 121 divides the data signals D0 to D15 into the two parts. Then, the control is performed such that the write operations are performed on the data signals D0 to D7 and then the write operations are performed on the data signals D8 to D15.
Specifically, the write operations will be performed below. That is, between the time 02 (FIG. 5) and the time t11 (FIG. 3), the write control circuit 121 supplies the control signal to the power supply circuit 105 in order to perform the write operation on the data signals D0 to D7. At the time t11 (FIG. 3), the gate boosting circuit 151 of the power supply circuit 105 applies a gate voltage (write voltage) Vpg1 that is the positive voltage, e.g., 9 V, to the control gate of the selection cell through the decoder 103 by the selection word line Ws in accordance with the control signal.
Between the times t12′ and t13′ shown in FIG. 6 corresponding to the times t12 and t13 in FIG. 3, the write control circuit 121 supplies the data signals D0′ to D7′ shown in FIG. 6 corresponding to the data signals D0 to D7, to the write circuits 161-0 to 161-7. Thus, as shown in FIG. 4, in the write circuits 161-0 to 161-7 of the write circuits 161-0 to 161-15, to which the data signals D0′ to D7′ are supplied, their N channel transistors are turned on, and the drain boosting circuit 152 and the selection bit lines BL1 to BL7 are connected through the write circuits 161-0 to 161-7.
At the time t12 (FIG. 3), the drain boosting circuit 152 of the power supply circuit 105 applies a drain voltage VDS0 that is the positive voltage of about (½) Vpg1, e.g., 5 V, to the drains of the selection memory cells through the write circuits 161-0 to 161-7, the column switch circuit 104 and the selection bit lines BL1 to BL7 in accordance with the control signal. At this time, source lines are grounded.
From those processes, between the times t12 and t13 (FIG. 3), the gate voltage Vpg1 becomes 9 V, and the drain voltage VDS0 becomes 5 V. As mentioned above, the write operations are performed on the selection memory cells. Here, the data is written to the selection memory cells for 8 bits (the regions 102-0 to 102-7) at the same time.
After that, between the times t14 and t15 (FIG. 3), the memory device is shifted to a sequence of verification and it is checked whether or not then the memory cell hast a desirable threshold voltage, for the selection memory cells into which the data is written. If the memory cell does not have the desirable threshold voltage, the rewrite operation at the write voltage (gate voltage) Vpg1 and the verification operation are repeatedly performed on only the memory cell in which the write operation is not sill completed. FIG. 3 shows the example in which the rewrite operation is not performed.
Prior to the time t15 (FIG. 3), the write control circuit 121 supplies the control signal to the power supply circuit 105 in order to perform the write operation on the data signals D8 to D15. At the time t15 (FIG. 3), the gate boosting circuit 151 of the power supply circuit 105 applies the gate voltage (write voltage) Vpg1 that is the positive voltage, e.g., 9 V, to the control gates of the selection memory cells through the decoder 103 and the selection word line W in accordance with the control signal.
Between the times t16′ and t17′ shown in FIG. 6 corresponding to a period between the times t16 and t17 shown in FIG. 3, the write control circuit 121 supplies the data signals D8′ to D15′ corresponding to the data signals D8 to D15 to the write circuits 161-8 to 161-15, as shown in FIG. 6. Thus, as shown in FIG. 4, in the write circuits 161-8 to 161-15 among the write circuits 161-0 to 161-15 to which the data signals D8′ to D15′ are supplied, their N channel transistors are turned on, and the drain boosting circuit 152 and the selection bit lines BLi connected to the write circuits 161-8 to 161-15 are connected. At the time t16 (FIG. 3), the drain boosting circuit 152 of the power supply circuit 105 applies the drain voltage VDS0 that is the positive voltage of about (½) Vpg1, e.g., 5 V to the drains of the selection memory cells through the write circuits 161-8 and 161-15 and the column switch circuit 104 and the selection bit lines BLi in accordance with the control signal. The source line is grounded.
From those processes, between the times t16 and t17 (FIG. 3), the gate voltage Vpg1 becomes 9 V, and the drain voltage VDS0 becomes 5 V. As mentioned above, the write operations are performed on the selection memory cells. Here, the data is written to the memory cells for 8 bits (the regions 102-8 to 102-15) at the same time.
After that, between the times t18 and t19 (FIG. 3), the operation is shifted to the sequence of the verification and then whether or not the memory cell has the desired threshold voltage is checked for the selection memory cells into which the data is written. If the memory cell does not have the desirable threshold voltage, the rewrite operation at the write voltage (gate voltage) Vpg1 and verification are repeatedly performed on only the memory cell where the write operation is not sill completed. In this way, the data corresponding to the 16 bits (the regions 102-0 to 102-15) are written at the times between t11 and t19.
In conjunction with the above description, Japanese Laid Open Patent Application (JP-P2001-52486A) discloses a flash memory device and a method of programming the same. In this conventional programming method, the flash memory device having an array of memory cells in a matrix is programmed. In this programming method, at least two memory cells among the memory cells are selected. Each of the selected memory cells is sequentially programmed to a predetermined threshold voltage lower than a target threshold voltage in a first time. The selected memory cells at the same time are programmed from the predetermined threshold voltage to the target threshold voltage in a second time. The flash memory device may be of the NOR type. The different drain voltages may be supplied to each of the columns corresponding to each of the selected memory cells in the second stage and the third stage.
Also, Japanese Laid Open Patent Application (JP-P2005-235287A) discloses a method of programming a nonvolatile semiconductor memory device, a programming apparatus, and a nonvolatile semiconductor memory device. In the method of programming the nonvolatile semiconductor memory device, applying a write pulse to a control gate of the memory element that has the control gate and a floating gate programs a memory element. That is, the write pulse is applied to the memory element while gradually increasing the write performance of the write pulse, until the threshold of the memory element becomes equal to or more than a first reference voltage. The write pulse has the write performance equal to or lower than the write performance of the write pulse finally applied at the above stage, until the threshold becomes equal to or more than a second reference voltage, and is applied to the memory element having a threshold that is higher than the first reference voltage and lower than the second reference voltage, after the above stage.
Also Japanese Laid Open Patent Application (JP-P2003-123491A) discloses a nonvolatile semiconductor memory device and a method of programming the same. This conventional nonvolatile semiconductor memory device includes a bit line, a first selection line, a first selection transistor, a word line, a nonvolatile memory cell transistor, a second selection line, a second selection transistor, a high voltage pump circuit, a selection line driver, a word line decoder and a slope control circuit. The first selection transistor has a control electrode connected to the first selection line and a current path whole one end is connected to the bit line. The word line is arranged adjacent to the first selection line and along with the first selection line. The nonvolatile memory cell transistor has a control electrode connected to the word line and a current path whose one end is connected to the other end of the current path of the first selection transistor. The second selection transistor has the control electrode connected to the second selection line and a current path whose one end is connected to the other end of the current path of the nonvolatile memory cell transistor and whose other end is connected to a ground voltage. The high voltage pump circuit generates a high voltage higher than a power supply voltage during a programming operation of the nonvolatile memory cell transistor. The selection line driver supplies a selection voltage to the first selection line during a period while the program voltage is supplied to the word line, and the selection voltage is limited to be lower than the power supply voltage. The high voltage and the selection voltage are supplied to the word line decoder, which supplies the program voltage to the word line. The slope control circuit controls a rising slope of the program voltage. The slope control circuit increases the program voltage during a predetermined period enough to protect the electrostatic coupling between the first selection line and the word line.
In the write sequence of the conventional nonvolatile semiconductor memory device of the NOR type that uses the CHE shown in FIG. 3, the data are preferably written to the memory cells for 16 bits at the same time. However, in case of using the CHE, the value of the write current flowing through the memory cell in the write sequence is relatively large. Thus, as shown in FIG. 3, the write operation is performed for each memory cells for 8 bits. That is, since the power supply circuit cannot supply the write current exceeding the current driver performance, this copes with it by limiting the number of the memory cells to which the write operations are performed at the same time, and then switching the memory cells of the write target in the write sequence. Therefore, the number of times of the write operation is increased, which results in a longer write time. A technique for shortening the write time is demanded. As a method of shortening the write time, a technique for increasing the power supply circuit and reducing the number of times of the write operation may be considered. However, this technique leads to a large circuit area of the power supply circuit and increases a chip area.
In Japanese Laid Open Patent Application (JP-P2001-52486A) is disclosed a technique for decreasing a circuit area of a power supply circuit. However, this technique has the following problems. FIG. 7 is a graph explaining the principle of the programming method in Japanese Laid Open Patent Application (JP-P2001-52486A). The vertical axis indicates a write current Ipg (a source—drain current), and the horizontal axis indicates a source—drain voltage VDS (hereinafter, to be referred to as [Drain Voltage VDS]). The memory cell can be regarded as a usual MOS transistor when viewed from a floating gate. Thus, the memory cell exhibits the standard drain current characteristic (the Id-VDS characteristic: corresponding to the Ipg-VDS in FIG. 2) as the MOS transistor shown in FIG. 2.
With reference to FIG. 7, the programming method in Japanese Laid Open Patent Application (JP-P2001-52486A) gives a sufficiently high gate voltage VG and controls the value of the drain voltage VDS and consequently obtains the desirable write current Ipg (for example, Iprc). That is, the operation is not performed in a saturation region A2 where independently of the value of the drain voltage VDS, the write current Ipg becomes substantially constant (Ipr), and it is performed in a transition region A1 where the write current Ipg can be controlled in the drain voltage VDS. At this time, for example, when the operation is performed under a drain voltage VDSC in FIG. 7, the write current is Iprc (<Ipr). However, in one memory cell array, it is not always possible to generate the same drain voltage VDSC for all of the memory cells. Thus, an error VDS of the voltage may be considered to be generated because of the relation of a manufacture yield. The error VDS directly causes the generation of a large error Iprc of the write current Ipg. That is, the error VDS of the drain voltage VDSC causes the write variation. A technique that can stably reduce the write time while suppressing the increase in the chip area is desired.